1. Field
Example embodiments may relate to an electronic circuit, and more particularly, to a multi-phase signal generator for generating pulse signals having a desired phase difference and a method thereof.
2. Description of the Related Art
Synchronous semiconductor devices may input/output data in synchronization with a clock signal. The synchronous semiconductor devices may include a clock signal generator, which generates an internal clock signal synchronized with an external clock signal.
When a semiconductor device inputs/outputs two bits (or symbols) of data per one data input/output terminal during a single clock cycle, the semiconductor device may include a quadrature phase signal generator, which may generate a multi-phase clock signal including pulses with a phase difference of 90 degrees with respect to an external clock signal.
Conventional quadrature phase signal generators may be implemented by a delay locked loop (DLL) circuit. A DLL circuit may include a voltage-controlled delay line (VCDL), and may generate an in-phase (or 0-degree) signal synchronized with an external clock signal and a quadrature phase signal having a 90-degree phase difference with respect to the external clock signal by adjusting a delay time of each delay element. However, since the DLL circuit may include a VCDL or delay elements connected in series, the circuit design may be complicated and the circuit may occupy a large area. Accordingly, a multi-phase signal generator that occupies a smaller area than the conventional DLL circuit, and/or one which may operate in a wider frequency range is desired.